“Brick and Mortar Chip Fabrication”, 2008 (; backlinks):
While Moore’s Law has advanced the semiconductor and technology industries, it has simultaneously driven up the cost of engineering a chip in a modern silicon process. The result is that fewer and fewer chips are produced in larger and larger volumes, stifling hardware diversity.
This thesis introduces brick and mortar chips, which aim to obtain the benefits of Moore’s Law without the financial side effects. Brick and mortar chips are made from small, pre-fabricated hardware components (called bricks) that are bonded in a designer-specified arrangement to a communication backbone chip which serves as the mortar (called the I/O cap). [cf. chiplet]
Our research examines several aspects of this chip manufacturing system. We develop a family of functional bricks, demonstrating a methodology for developing families that make efficient use of physical computation and communication resources. For high-performance communication between arbitrary combinations of bricks we propose a polymorphic on-chip network. This network allows a single I/O cap to be configured to implement the ideal network for any particular application. We analyze a low-cost, physical component assembly technique called fluidic self-assembly, and find that the chip production rate is intertwined with the architectural design of the components. To minimize application execution time on these partitioned chips, we develop software partitioning and mapping techniques which balance communication costs against computational resource contention.
We close with a case study: an analysis of a brick and mortar implementation of a chip multiprocessor. Despite this being a highly latency sensitive design, our measurements indicate a worst case 36% average slowdown in application execution compared to a traditional, monolithic chip. Based on this, our cost analysis, and a survey of related technologies, we conclude that brick and mortar offers the best available performance for its price.
…Technology scaling has produced a wealth of transistor resources and corresponding improvements in chip performance. However, these benefits come with an increasing price tag, due to rising design, engineering, and validation costs of modern chips.15 The result has been a steady decline in unique application-specific integrated circuit (ASIC) designs that enter production.21 This initiates a vicious cycle. Fewer unique chips means that fabs have fewer customers across which to amortize their costs, leading to even higher costs for those who do manufacture chips. The cycle completes as higher chip manufacturing costs exclude even more potential manufacturing customers.
While Moore’s Law has fueled the semiconductor industry, it has also fueled this spiral of increasing costs and shrinking fab customer bases. As transistors have shrunk, the cost of fabricating a semiconductor device has grown commensurately. While the fabrication cost per transistor has steadily declined,62 multiple other expenses have ballooned, contributing collectively to the growing total. For example, small features are more susceptible to process variation than larger ones, increasing the range of variation and the proportion of faulty chips. In addition, the smaller the transistor, the more of them that can fit in a given amount of silicon. The result is that circuit complexity has been increasingly out-stripping designer productivity, in a phenomenon referred to as Moore’s Law’s corollary of “compound complexity”.143
The industry has dealt with these challenges by increasing the engineering effort that goes into each chip. This effort manifests itself as larger design teams, or longer product cycles, and often both at once. The vast majority of this engineering effort is incurred once per chip design, and does not vary with the number of chips produced. Accordingly, this expense is called the non-recurring engineering cost (NRE) of a chip. Industry analysts estimate that the NREs for a typical 90 nm standard cell ASIC can range from $7.02$52008M up to $70.24$502008M.113
Maintaining a particular price..requires larger and larger batches of chips. This is because the single NRE is shared evenly across the population of chips produced. The larger the population, the smaller the impact of the NRE on individual chip cost…The result of this situation is that only high-volume chip manufacturers, or those who can sell smaller batches at high prices, can afford to be in the chip business. Moreover, at the same time that complexity and engineering effort have been soaring, the commercial market has been demanding and rewarding short chip design cycles. This is due to shrinking product lifetimes and the increasing competitive importance of being the first to market with a new product…One of the inputs is the assumed NRE. The NRE includes all engineering effort…with an engineer’s time costing upwards of $533,831.81$380,0002008 per year,141 the engineering cost is nearly always a 7-figure number…NREs also encompass the cost of tools, IP licenses if necessary, and photolithographic masks. ASIC design tools typically cost more than $421,446.16$300,0002008.146 Mask cost has been roughly doubling every technology node, resulting in a complete set of 90 nm masks costing between $1.4$12008M and $4.21$32008M.146…In 2000, the cost to test each transistor was 10% of the cost to manufacture it. However, as transistors become cheaper and testing becomes more difficult, it is projected that by 2015 it will cost more to test a transistor than to make it.73
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