“Loihi: A Neuromorphic Manycore Processor With On-Chip Learning”, 2018-01-16 ():
Loihi is a 60-mm2 chip fabricated in Intel’s 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally Competitive Algorithm, Loihi can solve LASSO optimization problems with over 3 orders of magnitude superior energy-delay-product compared to conventional solvers running on a CPU iso-process/voltage/area. This provides an unambiguous example of spike-based computation, outperforming all known conventional solutions.
[Keywords: neuromorphic computing, machine learning, artificial intelligence, IBM, spiking neural networks, ASICs, SNN, Loihi]
…Spiking Neural Networks: We consider an SNN a model of computation with neurons as the basic processing elements. Different from ANNs, SNNs incorporate time as an explicit dependency in their computations. At some instant in time, one or more neurons might send out single-bit impulses, the spike, to neighbors through directed connections known as synapses, with a potentially non-zero traveling time. Neurons have local state variables with rules governing their evolution and timing of spike generation. Hence, the network is a dynamical system where individual neurons interact through spikes
…Chip Overview: Loihi features a many-core mesh comprising 128 neuromorphic cores, 3 embedded x86 processor cores, and off-chip communication interfaces that hierarchically extend the mesh in 4 planar directions to other chips. An asynchronous network-on-chip (NoC) transports all communication between cores in the form of packetized messages. The NoC supports write, read request, and read response messages for core management and x86-to-x86 messaging, spike messages for SNN computation, and barrier messages for time synchronization between cores. All message types may be sourced externally by a host CPU or on-chip by the x86 cores, and these may be directed to any on-chip core. Messages may be hierarchically encapsulated for off-chip communication over a second-level network. The mesh protocol supports scaling to 4096 on-chip cores and, through hierarchical addressing, up to 16,384 chips.
Each neuromorphic core implements 1,024 primitive spiking neural units (compartments) grouped into sets of trees constituting neurons. The compartments, along with their fan-in and fan-out connectivity, share configuration and state variables in 10 architectural memories. Their state variables are updated in a time-multiplexed, pipelined manner every algorithmic time-step. When a neuron’s activation exceeds some threshold level, it generates a spike message that is routed to a set of fan-out compartments contained in some number of destination cores.